In synchronous dynamic random access memory (SDRAM) applications, the inherent analog delay between an external, system or reference clock and the time output data is always a concern. Even a slight delay may be large enough to make a following clock cycle overlap the data, thus causing the data not to be ready at the output during one cycle. This inherent internal delay must therefore be selectively accelerated according to the necessary frequency to resolve the problem. This leads to a new problem of achieving synchronization between the internal clock, which controls the output path, and the correct edge of the external clock. This is often referred to as a “Lock Latency”, which is defined as relative time displacement between a given external clock edge (parent) and the associated internal DLL generated clock edge (child).
Conventional double data rate (DDR) synchronous dynamic random access memories (SDRAM) employ a plurality of delay locked loop circuits (DLL). These DLL circuits are employed to synchronize delay between two signals, such as the clock signal and a delayed clock signal. Analog delay locked loops have been employed in the past to perform the synchronization, which are comprised of a delay chain having the delay of its elements varied by analog bias voltages supplied by a phase detector. In digital systems such as memories, microprocessors and application specific integrated circuits, these types of delay locked loops introduce analog design complications in a mainly digital design, and therefore are avoided. Digital delay locked loops use a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital delay locked loops have a much higher jitter than analog delay locked loops, their ease of implementation in a digital system makes them the preferred solution in most digital applications. As digital delay locked loops become more prevalent, the need increases for a method and apparatus that can process transmitted/recieved signals synchronously with an I/O data stream.